R1621 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n fast ethernet risc processor specifications subject to change without notice, contact your sales representatives for the most update information. page 1 of 4 rev 1.0 aug. 18 2005 r r 1 1 6 6 2 2 1 1 b b r r i i e e f f s s h h e e e e t t f f a a s s t t e e t t h h e e r r n n e e t t r r i i s s c c p p r r o o c c e e s s s s o o r r
R1621 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n fast ethernet risc processor specifications subject to change without notice, contact your sales representatives for the most update information. page 2 of 4 rev 1.0 aug. 18 2005 1. features l cpu core - rdc's proprietary risc architecture - five-stage pipeline - operation frequency: 100mhz - supports an 8k-byte uniform cache - supports cpu id - supports 40 pio pins l bus interface - supports non-multiplexed address bus a[19:0] - with 8-bit or 16-bit boot rom bus size - supports an independent data/address bus for external i/o devices - 8-bit or 16-bit external bus dynamic access l pcmcia bus interface - supports a glueless and simplified 16-bit pcmcia bus interface l rom/ram/sdram controller and addressing space - supports 16-bit data bus [15:0] - 1m-byte memory address space address[19:0] - sdram control interface - 64k-byte i/o space l compatible uart channels - supports two compatible uart serial channels with 16-byte fifos and hardware flow-control l two independent dma channels l fast ethernet mac ports - 2-port fast ethernet mac with mii interface - the mac packet buffer is cacheable with snooping function l interrupt controller - the interrupt controller with five maskable external interrupts l programmable chip-select logic - programmable chip-select logic for memory or i/o bus cycle decoder l programmable wait-state generators l counter/timers - three independent 16-bit timers and one independent programmable watchdog timer l operating voltage range - core voltage: 2.5v 5% - i/o voltage: 3.3v 10% l package type 128-pin pqfp
R1621 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n fast ethernet risc processor specifications subject to change without notice, contact your sales representatives for the most update information. page 3 of 4 rev 1.0 aug. 18 2005 2. block diagram dma unit chip select unit refresh control unit sdram/bus interface unit pio unit timer control unit interrupt control unit clock and power management 16550 uart serial port0 instruction queue (64bits) instruction decoder register file general, segment, eflag register alu (special, logic, adder, bsf) micro rom ea / la address control signal execution unit x1 x2 clkouta int6-int5 int0 drq0 drq1 sout0 sin0 a[19:0] d[15:0] ale bhe_n vcc gnd mcs_n ucs_n pcs5_n pcs3_n pcs2_n pcs0_n ardy rd_n 16550 uart serial port1 int1 int2 rst_n mac0 mac1 mii 1 mii 0 sd_clk we_n cas_n ras_n ba[1:0] dcd0_n dtr0_n dsr0_n rts0_n cts0_n ri0_n sout1 sin1 dcd1_n dtr1_n dsr1_n rts1_n cts1_n ri1_n wr_n/bwsel cache pio[39:0]
R1621 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n fast ethernet risc processor specifications subject to change without notice, contact your sales representatives for the most update information. page 4 of 4 rev 1.0 aug. 18 2005 3. package information pqfp 128 pins seating plane 1 38 128 103 65 102 64 39 pin 1 identifier 3.40mm (max.) 0.25mm (min.) 0.145 0.055mm 0.5mm bsc 1.60mm 0.25mm detail a detail a 3.40mm (max.) 2.85 0.12mm 0.88 0.15mm 2.85 0.12mm 0.22 0.05mm 17.2 0.2mm 14.0 0.1mm 20.0 0.1mm 23.2 0.2mm 0.17~0.27mm
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